1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same, and in particular to a double-diffused MOSFET and a method of fabricating the same.
2. Description of the Related Art
There is known a double-diffused MOSFET (referred to as DMOSFET, hereinafter) as a MOS transistor operable at a voltage around 100 V. As shown in FIG. 25, the DMOSFET has, as being formed over the entire surface of a P-type semiconductor substrate 1, an N-type buried layer 2 in which a diffused region 2b, an N-type, heavily-doped buried layer 2a and a diffused region 2b are stacked in this order, and has a drain region 7 formed by growing an epitaxial layer on the N-type buried layer 2. The drain region 7 has, as being formed therein, a drain extraction region 9 and a drain contact layer 12 containing an N-type impurity diffused therein, and a P-type body region 10 containing a P-type impurity diffused therein. The P-type body region 10 has an N-type source region 13 formed in the surficial portion thereof, and additionally has a P+-type region 14 formed as being surrounded by the N-type source region 13. The region between the N-type source region 13 and the drain extraction region 9 has a drift region and a field oxide film 8, and also has a gate electrode 11 formed thereon so as to cover the drift region and a part of the field oxide film 8, while placing a gate insulating film in between.
The DMOSFET can be fabricated by a general diffusion process, and is used in combination with various MOSFETs by virtue of its convenience for IC manufacturing, because all terminals of which can be extracted from the top surface of the chip. For example, Patent Publication Laid-Open 1994-37266 discloses a structure of an integrated circuit in which a CMOSFET for logic circuit is hybridized with a high-voltage-resistance DMOSFET, and a method of fabricating the same.
In thus-configured DMOSFET, the drain resistance may be lowered by raising the impurity concentration in the N-type buried layer 2, but increase in the impurity concentration of the N-type buried layer 2 undesirably makes it more likely to cause punch-through between the source and drain, and fails in keeping a desirable level of the drain voltage resistance. A problem therefore remains in that any effort of keeping the drain voltage resistance at as high as 80 V or around results in only an insufficient reduction in the drain resistance, and consequently fails in obtaining transistors with desirable characteristics.
The impurity concentration of the N-type buried layer 2 might slightly be increased for the case where the DMOSFET is used as a device having a voltage resistance of as low as 20 to 40 V or around, and thereby the drain resistance might be reduced to some degree, but a problem arises even in this case in that the N-type impurity causes out-diffusion from the N-type buried layer 2 when the epitaxial layer is grown thereon, and causes auto-doping into the epitaxial layer.